1.14 bit address, 7 for column, 7 for the rows.

2.Only 1 data bit out.

1.With DRAM, the 7 address bits for the row and column come on one multiplexed address bus.

2.Still only 1 data out bit.

1.Really this is only one half of the 30 pin SIMM.

2.30 pin SIMM has an 8 bit data bus/path.

1.For each read we need one CAS and one RAS.

2.Once data is present, CAS & RAS must be turned off.

3.CAS & RAS must recover (precharge) before the next read.

4.Latency is sum of Access time and cycle time.

5.Access time is from Row Address signal to Data out.

6.Cycle time is recovery time.  I.e. RAS precharge.

7.

1.  CAS for Col 2 can not start until Data 1 is gone.

1.CAS can overlap previous Data.  Thanks to new technological advances.

2.Bus speeds now go to 66 MHz.

3.Still need CAS.  WHY?  Because DRAM, FPM and EDO are asynchronous.

4.Still need a CAS for each column strobe.

5.Takes tRAC & RAS Precharge out of the critical timing path.

6.Speeds of 6-3-3-3 now available as a four column burst.

1.Everything before was 486 or older and non synch.  Now we get into the Pentium class machines.

2.BA0 identifies which bank is active.

3.Since this synchronized with the system clock, CAS is needed only for the first address of the burst.

4.Bus speeds now are at 133MHz and faster.

1.Explain the difference between Nop and Wait state.

2.This shows how the Nop delays the data until the system is ready for it.

1.Each chip can have up to 32 Data pins.  For this example I use 16 data pins per chip.

2.Each Bank can have only one active page (row).  With this example, we can have one active row with data coming out and three active rows waiting for a CAS.

3.DDRRAM is basically the same, but has additional circutry to allow data to be presented on both the leading and trailing edges of the clock pulse effectively doubling the bus frequency.

1.This diagram is for the 1 meg chip.

2.Each bank = 512 rows of 128 Dualocts.

3.A dualoct is the smallest unit of addressable memory.

4.A dualoct is 16 bytes of memory.

5.RAMBUS chips can have 16 or more banks, depending on the chip size.

6.Each bank = 512 Rows of 128 Dualocts.

7.A Dualoct is the smallest unit of memory addressable.

8.Chips can have 16 or more banks.

1.This shows how we convert the dualoct into a Data Packet of 2 bytes wide by 8 bytes long.

2.Notice that the Clock is only 400 MHz, but is using both the leading and trailing edges to transfer data.

3.Notice the RAMBUS Data Bus is only 16 bits wide verses 64 bits on the DDRRAM bus.

1. Now, lets do some math.

2. RDRAM, 800MHz @ 2 Bytes = 1600 Mbytes/Sec

3. SDRAM, 100MHz @ 8 Bytes = 800MBytes/Sec

4. SDRAM, 200MHz @ 8 Bytes = 1600MBytes/Sec

5. SDRAM, 266MHZ @ 8 Bytes = 2132 Mbytes/Sec.

6. 16 active banks per chip, 4 chips per module = 64 open banks per RDAM vs.4 banks per module and 4 modules = 16 banks active on the SDRAM

1. On the SDRAM the path for memory is a short trip from the memory address directly   to the controller.

2. On the RDRAM the path I serial and goes through every module.  This could add to the latency of the system.

3.Also note, that if all sockets are not filled with memory modules, then Continuity modules must be used.

1.  30 Pin SIMM with 1 Data pin per chip = 8 Bit Bus

2.  72 Pin SIMM with 8 Data pins per chip = 32 Bit Bus 

3.  168 Pin DIMMs (not shown) have 64 Bit Bus