1.Each chip can have up to 32 Data pins. For this example I use 16 data pins per
chip. |
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2.Each Bank can have only one active page
(row). With this example, we can have
one active row with data coming out and three active rows waiting for a CAS. |
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3.DDRRAM is basically the same, but has
additional circutry to allow data to be presented on both the leading and
trailing edges of the clock pulse effectively doubling the bus frequency. |